Transistors such as metal oxide semiconductor field effect transistors (MOSFETs) or simply field effect transistors (FETs) or MOS transistors are the core building blocks of the vast majority of semiconductor integrated circuits (ICs). A FET includes source and drain regions between which a current can flow through a channel under the influence of a bias applied to a gate electrode that overlies the channel. The ICs are usually formed using both P-channel FETs (PMOS transistors or PFETs) and N-channel FETs (NMOS transistors or NFETs) and the IC is then referred to as a complementary MOS or CMOS circuit.
Certain improvements in the performance of MOS ICs can be realized by forming the MOS transistors in a thin layer of semiconductor material (semiconductor layer) overlying a buried insulator layer that overlies a support substrate (e.g., silicon substrate). Such semiconductor or silicon-on-insulator (SOI) MOS transistors, for example, exhibit lower junction capacitance and can operate at higher switching speeds than MOS transistors formed in bulk substrates. In SOI MOS transistors, the semiconductor layer, in which the source and drain regions are formed, is dielectrically encapsulated. In particular, the MOS transistors are typically enclosed in an interlayer dielectric material that overlies the semiconductor layer, which overlies the buried insulator layer. This configuration provides significant advantages but also give rise to certain issues.
One issue is the build up of static surface charges on the SOI substrate. In particular, the support substrate of the SOI substrate is typically not electrically connected to any other structure. The SOI substrate is “floating” over the support substrate due to the presence of the buried insulator layer; thus static surface charges may easily build up on the SOI substrate during IC fabrication and/or normal IC operation. These static charges may undesirably disturb the normal operation of the IC or devices in the IC. Further, current IC manufacturing approaches for grounding to prevent or minimize the build up of these static surface charges can involve a significant number of additional manufacturing processes including the use of additional etching masks, etching and/or deposition processes to create an electrical pathway(s) or substrate contact(s) for transporting static surface charges through the buried insulator layer between the semiconductor layer and the backside support substrate of the SOI substrate.
Accordingly, it is desirable to provide methods for fabricating integrated circuits including silicon-on-insulator (SOI) substrates with reduced manufacturing complexity and/or enhanced manufacturing efficiency for forming substrate contacts. Furthermore, other desirable features and characteristics of the present embodiment will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and this background.